1. Field of the Invention
The present invention relates to a flip chip packaging structure and method of a semiconductor integrated circuit and, in particular, to a flip chip packaging structure and method of an image sensor.
2. Description of the Related Art
Multilayer packaging is one of the most advanced processes for fabricating semiconductor integrated circuit (IC) products. With the multilayer package, the space between the electrodes of an IC chip having multilayer package electric circuits is increased; the chip is protected from the internal stresses of the package and any external stresses, and an appropriate thermal path for dissipating heat generated by the chip and an electrical interconnection are established. The method for packaging an IC chip is deemed as the system used for the package, dominating the total cost, performance and reliability of the whole package chip.
IC chip packaging generally falls into two categories, that is, hermetic packages and non-hermetic packages. When a chip is packaged by the hermetic package, it is isolated from the external environment by a vacuum seal or a particular kind of gas surrounding the chip. In general, such hermetic packages are the ceramic packaging used for high efficient applications. In other words, when a chip is packaged by the non-hermetic packages, it is not substantially isolated from the external environment. In this light, the hermetic packages have higher fabrication cost than the non-hermetic packages. Even so, the hermetic packages are still needed in some particular applications such as image sensors or pressure detectors. The recently advanced application with the plastic packaging has expanded the scope of usage and the performance of the hermetic packages. Since the traditional method for fabricating products is good for automatic batch processing, the plastic packages are highly cost-effective.
An IC chip packaging recently developed is ball grid array (BGA) packages, which can be used for both the ceramic packaging and the plastic packages. The BGA packages use a plurality of solder balls or bumps to serve as interconnections between the IC chip and other micro electronic devices providing electricity, mechanical support or heat transfer. The solder balls or bumps cause the IC chip to be fixedly mounted on a circuit board, and are electrically connected with the conductive pattern of the circuit board. The BGA techniques are included in the bonding technology defined as the controlled collapse chip connection (C4) or the flip chip technology.
The flip chip technique can be used to bond various circuit boards comprising a ceramic substrate, a printed circuit board, a flexible circuit and a silicon substrate. The solder bumps are generally disposed on a conductive bond pad of an area array of a flip chip, the conductive bond pad being electrically interconnected to an electric circuit trace on the flip chip. Since micro-electric circuits of the flip chip will generally perform various functions, a number of solder bumps will therefore be required. As a rule, each side of the flip chip has a size of about 13 mm, resulting in solder bumps jammed on the perimeter of the flip chip. Thus, the conductive pattern of the flip chip is consisted of various conductors spaced apart appropriately equal to or less than 0.1 mm as a matter of course.
Leadless chip carrier (LCC) packages are generally found in an image sensor such as a charge coupled device (CCD) image sensor or a complementary metal oxide semiconductor (CMOS) image sensor.
The CCD image sensor is an electronic device capable of converting an optical pattern or image into a charged pattern or an electronic image, comprising a number of photosensitive units capable of modifying, storing and transferring a charge to another photosensitive unit. In designing an image sensor, the material is selected subject to the photosensitivity of silicon. Each photosensitive unit represents a pixel. Semiconductor technologies and design rules dominate the array structure and matrix structure of the pixels. Signal output from the CCD is modified by means of one or more than one amplifier disposed on the edge of the chip. An electronic image is obtained by a series of pulses which sequentially output the charge of one pixel in array after another pulse is output to an output amplifier. Then, the output amplifier converts the charge into a voltage. An external electric circuit transfers an output signal in an appropriate form for detection or pick-up.
The CMOS image sensors operate at a voltage lower than the CCD image sensor so as to reduce power consumption and facilitate the portability. Each CMOS active pixel sensing unit has an amplifier with buffering capability for reading/writing separately. A conventional pixel sensing unit has four transistors and a photosensitive unit. The pixel sensing unit has a transfer gate for separating the photosensitive unit from a floating diffusion having a capacitance, a reset gate interposed between the floating diffusion and a power supply, a source-follower transistor for temporarily storing the capacitance of a read-out line in the floating diffusion, and a row of select gates for connecting the pixel sensing unit to the read-out line. All the pixels connected in column -are connected to a shared sense amplifier.
In comparison with the CCD image sensor, the CMOS image sensor not only reduces power consumption but also has a generally simple scheme due to decoupling and crystallization characteristics. Hence, a miniature CMOS image sensor is easy to design, requiring fewer circuits in support thereof.
FIG. 5 shows a traditional leadless chip carrier package 30 which is generally used for a CCD or CMOS image sensor IC chip. The leadless chip carrier package 30 comprises a transparent cap layer 32 made of glass having a supporting layer 35. An anti-reflection coating 34 is interposed between the glass cap 32 and the supporting layer 35. A multilayer substrate 36 has a castle-shaped structure 42 with an image sensor chip 38 provided thereon. An upper lead 40 extends from the chip 38 to be electrically connected to a lower lead 44 encased on the bottom and the sides of the substrate 36. The transparent glass cap 32 facilitates light transmission to the image sensor chip 38.
The leadless chip carrier package 30 generally has a thickness 46 of about 2 mm. When the leadless chip carrier package 30 is used for the image sensor package 30, a relatively large space is required. In most cases, an over-sized image sensor restricts the utilization of the leadless chip carrier package 30. In this light, there is a dire need to provide the image sensors with a new and improved packaging structure and method.